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    TIEC and VLSI Egypt Offer the “Industrial Challenges of Advanced Analog Design in Deep Submicron Process Technologies”

    Date published: 18 July 2012
    As TIEC proceeds with fulfilling its mission in encouraging innovation and supporting innovators, TIEC in collaboration with VLSI Egypt offered an Analog Design Course on 18 July 2012, at its premises at Smart Village.
    The course title is “Industrial Challenges of Advanced Analog Design in Deep Submicron Process Technologies”

    Designing analog circuits on deep sub-micron process technologies (32, 22, 14, 10, 7, 5 nm) has its own set of challenges. With supply voltage scaling down, threshold voltages holding its values to maintain moderate leakage currents as demanded by low power designs for modern and mobile gadgets, the headroom is running out.
    Coupled with degraded rout and denser metal stack, stringent design and density rules make analog design even tougher, especially for high yield products that are required to ship hundreds of millions of units with very low wafer cost.

    This focused class is intended to address these challenges from an industrial view point, starting from the basics, building its way up to designing advanced analog blocks in deep submicron process nodes, while keeping yield as the number one challenge.

    The course covered several topics such as what to expect out of the fellow transistor in 22nm and beyond as well as the device matching consideration. It will also present the building block design in deep sub-micron in addition to the different topologies of bias circuitry and many other different topics.

    This course targeted senior undergrads and EE graduates working in the VLSI Field. The course was conducted by Dr. Ahmed Helmy (Sr. Staff Design Manager at Intel).

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